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Making Quality A Top Priority in Next-Generation Designs

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not...

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Restrictive Design Rules, Take Two

By Ed Sperling For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for...

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End User Report: Things To Do With Multicore

System-Level Design sat down with Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia, to talk about changes in the communications sector and how that’s...

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Making DFM Work Better

By Ann Steffora Mutschler At 65nm, design for manufacturing optimization and analysis has mostly been an afterthought. At 40nm and beyond, DFM has been pushed well up into the design phase. There are...

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Weary Chip Designers Must Embrace Manufacturing

By John Blyler The essence of Design for Manufacturability or DFM is to ensure that what is designed can be manufactured. The challenge is that both processes – design and manufacturing – use different...

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More Design Rules Ahead

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two...

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Keeping Pace With Moore’s Law

By Ann Steffora Mutschler As the number of transistors doubles with each move to a smaller manufacturing process technology, there are questions as to whether the current cadre of place and route tools...

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The Week In Review: May 3

By Ed Sperling ARM licensed 138 Sonics patents, including those affecting on-chip interconnects and agreed to support Sonics’ forthcoming power management technologies. The deal goes a long way toward...

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Heads Up: DAC

By Ed Sperling The Design Automation Conference turns 50 this year. In that time it has grown from a tiny conference whose existence and value were in question into a mainstay of the semiconductor and...

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DAC Minus One

By Ed Sperling DAC officially begins this morning, five decades after it first began—only this time the celebration is more likely to involve a barbecued steer than a glass of red wine from Napa...

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The Week In Review: July 12

By Ed Sperling Cadence rolled a new version of its layout suite of tools for electrically aware designs, allowing design teams to check on electrical issues while the layout is being done. The company...

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Making Quality A Top Priority in Next-Generation Designs

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not...

View Article

The Week In Review: Aug. 16

By Ed Sperling Manufacturing Equipment giant Applied Materials added three extra letters company president Gary Dickerson’s title—CEO. Mike Splinter, who has served as the company’s CEO since 2003,...

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The Week In Review: Sept. 6

By Ed Sperling ARM acquired Cadence’s high-resolution display processor cores, which it helped to co-develop. Coupled with ARM’s own graphics, the move sets up ARM to sell complete subsystems. Cadence...

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An EDA View of Semiconductor Manufacturing

Gabe Moretti, Contributing Editor The concern that there is a significant break between tools used by designers targeting leading edge processes, those at 32 nm and smaller to be precise, and those...

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What Is Not Testable Is Not Fixable

Gabe Moretti, Senior Editor In the past I have mused that the three letter acronyms used in EDA like DFT, DFM, DFY and so on are superfluous since the only one that counts is DFP (Design For Profit)....

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Power Analysis and Management

Gabe Moretti, Senior Editor As the size of a transistor shrinks and modifies, power management becomes more critical.  As I was polling various DA vendors, it became clear that most were offering...

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